1. Field of the Invention
The present invention relates generally to semiconductor integrated circuits and more specifically to a method of placing a plurality of integrated circuit chips on a semiconductor wafer.
2. Description of the Related Art
The computer-assisted design of a semiconductor device (LSI) usually proceeds through a number of stages each involving the use of layout data for the placement of circuit elements on a semiconductor wafer. A layout design of LSI includes a number of processes such as a floor-plan layout process for the determination of location of logic circuit elements, a deployment process for the placement of circuit elements, and a wiring process for the determination of routes for interconnecting the circuit elements. Signals that flow through an interconnection experience a propagation delay. Because of the numerous factors associated with complex fabrication processes, variability exists in propagation delay time between different IC chips. In order to reflect the variability of propagation delay times on LSI design, minimum, normal and maximum delay times of various interconnections are stored in a memory to be used as a library of delay values. However, there is still delay time variability between interconnections within the same semiconductor chip. Delay time variability within a chip includes a position-dependent delay component that varies gradually from one location to another over the surface of the chip. Usually, the position-dependent delay component is caused by a non-uniform thermal distribution or Gaussian noise over the wafer surface during fabrication. The delay time variability also includes a random delay component that occurs randomly over the wafer surface regardless of its surface point. The delay time variability is thus represented by a combined effect of the delay time variations of position-dependent component and those of random component. Details of such delay time variability are discussed in a technical paper titled “Layout Dependent Matching Analysis of CMOS circuits”, K. Okada et al, IEIECE Transactions on Fundamentals, Vol. E82-A, No. 2, pages 348 to 355.
Japanese Patent Publication 2001-350810 teaches the use of a library of variances (or standard deviations) of delay time variations to be used for LSI design in order to adapt the interconnection delay time variations of an LSI chip to delay-time variability between different chips. In the disclosed library, the delay time variations of position-dependent component of logical circuits and their delay time variations of random component are stored in addition to average delay times which have hitherto been obtained in known manner.
However, there is still a need to improve the design method of a semiconductor device. Part of the delay time variations of position-dependent component of a wafer is accounted for by delay components generated as a result of the chip-pattern forming process performed by the stepper. In this process, a small region of a semiconductor wafer is exposed to a beam of radiation through a photomask (known as a reticle) and the wafer is moved stepwise to the next region. The process is continued until the same circuit pattern is copied to all regions of the wafer. Since it is likely that all the stepwise pattern forming processes have physical factors in common that affect device performance in terms of delay time, the circuit patterns copied on the wafer tend to share the same physical features. As a result, it is considered that variability of device parameters due to different threshold levels and different turn-on currents account for delay time variations of exposure-dependent component. One of the probable causes of variability is the aberrations of optical lenses of the stepper. Due to the lens aberration, the resolution of a chip pattern on the wafer surface degrades variably depending on the distance from the optical axis of the lens system. Therefore, each of the chip patterns on the wafer exhibits structural variability having a distribution of concentric patterns that differ as a function of distance from the optical axis of the lens system, so that similar structural features can be observed at points spaced at equal distances from the center of the concentric patterns.
FIG. 1 is a graphic representation of delay characteristics of a test chip for evaluation of device parameters on a wafer. The delay characteristics are represented by the flow of current measured as function of distance along the radial direction of the wafer. The solid lines represent distributions of delay times along the radial direction and the broken line represents the delay times of position-dependent component of such delay time distributions. Delay time differences between the radial components and the position-dependent component are delay times of exposure-dependent component. For the purpose of discussion, the delay times of random component are ignored. If the test chip is located only in a particular fixed position of the wafer, the measurement will result in either an overestimated value or an underestimated value. For example, if the test chip is located at one of the points A (where the delay time is minimum), the measured delay times are underestimated values as compared to the delay times of other chips on the same wafer. Conversely, if the test chip is located at one of the points B (where the delay time is maximum), the measured delay times are overestimated values as compared to the delay times of other chips on the same wafer.
However, the prior art integrated circuits were not designed with delay time values of radiation (exposure) dependent component in mind. Thus, need exists to improve the performance of integrated circuits by taking into account exposure-dependent delay time values of logic gates.